1. Field of the Invention
The present invention relates to a semiconductor device with a memory cell composing a transistor and a thyristor in a reduced cell area.
2. Description of the Related Art
Attempts have long been made to assemble memory from elements having negative-resistance characteristics, because the resulting memory would represent “zero” and “one” according to the two states—high resistance and low resistance—which the negative-resistance element assumes.
There has recently been proposed a new memory cell which composes a thyristor (as a negative-resistance element) and an access transistor serially connected thereto, said thyristor being controlled (for turn on and turn off) by a gate electrode formed thereon. This memory cell will be referred to as T-RAM memory cell hereinafter. See, U.S. Pat. No. 6229161 (B1) and Farid Nemati and James D. Plummer “A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-Scale Memories” Technical Digest IEDM 1999, p. 283-286. (Hereinafter referred to as Patent Document 1 and Non-Patent Document 1)
The T-RAM memory cell mentioned in Non-Patent Document 1 will be described below with reference to FIG. 5 attached hereto. In FIG. 5, there is shown a thyristor 120 which has the vertical pnpn junction. The thyristor 120 has an n-type emitter 121 connected to an n-type diffused layer 142 of an access transistor 140 and also has a gate electrode 125 which is arranged on the p-type base 122 by MIS structure.
The T-RAM memory cell mentioned in Non-Patent Document 1 is represented by an equivalent circuit shown in FIG. 6. It is to be noted that the gate electrode 245 of the access transistor 240 is connected to the word line WL1, the gate electrode 225 of the thyristor 220 is connected to the word line WL2, one diffused layer 241 of the access transistor 240 is connected to the bit line BL, the other diffused layer 242 of the access transistor 240 is connected to the n-type emitter 221 of the thyristor 220, and the p-type emitter of the thyristor 220 is connected to the reference voltage (Vref).
The T-RAM memory cell holds data due to the characteristics shown in FIG. 7. When the voltage (Vref) at the anode of the thyristor is kept high with respect to the bit line BL, “zero” is represented by the intersection of the high-resistance characteristic curve of the thyristor and the characteristic curve of the access transistor and “one” is represented by the intersection of the low-resistance characteristic curve of the thyristor and the characteristic curve of the access transistor.
The T-RAM memory cell permits data reading owing to the characteristics shown in FIG. 8. When a reading voltage is applied to the word line WL1 (so that the access transistor decreases in resistance) and the voltage (Vref) at the anode of the thyristor is made high with respect to the bit line LB, “zero” is represented by current at the intersection of the high-resistance characteristic curve of the thyristor and the characteristic curve of the access transistor and “one” is represented by current at the intersection of the low-resistance characteristic curve of the thyristor and the characteristic curve of the access transistor.
The T-RAM memory cell writes a data value of “one” by the characteristics shown in FIG. 9. This step is accomplished when a writing voltage is applied to the word lines WL1 and WL2 and the voltage of the bit line BL is made lower than the voltage (Vref) at the anode of the thyristor so that the thyristor assumes the low-resistance state.
The T-RAM memory cell writes a data value of “zero” by the characteristics shown in FIG. 10. This step is accomplished when a writing voltage is applied to the word lines WL1 and WL2 and the voltage of the bit line BL is made higher than the voltage (Vref) at the anode of the thyristor so that the thyristor assumes the high-resistance state.
As mentioned above, the T-RAM memory cell composes one bit with one access transistor and one thyristor.
There has recently been proposed a technology for forming memory cells on an SOI substrate. (See Non-Patent Document 1.)
The thyristor-based memory cell structure mentioned above suffers the disadvantage of demanding a special process to realize the vertical thyristor. Also, the memory cell on an SIO substrate suffers the disadvantage of demanding an expensive SIO substrate and involving difficulties not encountered in ordinary bulk substrates.
The memory cell to be formed from a thyristor and an access transistor on a bulk substrate poses the following problem. The thyristor 120 is composed of a p type impurity layer (anode), an n type impurity layer (n type base), a p type impurity layer (p type base), and an n type impurity layer (cathode), which are formed vertically to give the p/n/p/n junction. When this thyristor is turned on and off, a vertical parasitic thyristor is formed by the p type impurity layer (anode), the n type impurity layer (n type base), the p type impurity layer (p type base), and an n type well in an n type impurity region formed under the p-type impurity layer (p type base). This vertical parasitic thyristor becomes on and off as the thyristor 120 is turned on and off, which causes holding current to flow through the deep n type well when a data value of “one” is held in the turn-on state.
The disadvantage of the memory cell formed on a bulk substrate is that the p-type base layer of thyristors has to be electrically divided for individual memory cells, which leads to a large element separating width (and hence a large cell size). This will be explained briefly below. The p-type base layer for thyristors has to be electrically separated for individual cells. A certain electrical distance is necessary between the p-type base layer and the p-type well of the access transistor. A certain width of element separation is necessary for possible disalignment and variation in line width of register pattern that would occur when implantation is performed to form the p-type base layer and the p-type well of the access transistor. This is the cause of the large element separating width and the large cell size.